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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD1981A one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 ac ?7 soundmax codec functional block diagram ac 97 2.2-compliant codec features s/pdif output, 20 bits data format, supporting 48 khz and 44.1 khz sample rates integrated stereo headphone amplifier variable sample rate audio external audio power-down control greater than 90 db dynamic range 16-bit stereo full-duplex codec 20-bit dac input three analog line-level stereo inputs for line-in, aux, and cd mono line-level phone input mono mic input with built-in programmable preamp high quality cd input with ground sense mono output for speakerphone or internal speaker power management support 48-lead lqfp package enhanced features built-in digital equalizer function for optimized speaker sound full duplex variable sample rates from 7040 hz to 48 khz with 1 hz resolution jack sense pins provide automatic output switching software-programmed v refout output for microphone bias and external power amp split power supplies: 3.3 v digital and 5 v analog multiple codec configuration options soundmax is a registered trademark of analog devices, inc. eq coeff storage ac ?7 control registers 16-bit - a/d converter 16-bit - a/d converter jack sense analog mute control logic mic_in cd_l cd_gnd cd_r line_in hp_out_l line_out_l mono_out line_out_r hp_out_r aux phone_in hp a m a m hp a m mic preamp g a a selector selector cd diff amp m ga js0 js1 m ga m ga m ga m ga m m m m m ga m ga m g m g m g m g v refout xtl_out xtl_in id1 id0 xtal oscillator pll clock generator link port/ id select a/d sample rate generator 20-bit - d/a converter 20-bit - d/a converter 16-bit - a/d converter d/a sample rate generator 16-bit - a/d converter ac ?7 link signals ac ?7 serial interface spdif spdif AD1981A eapd eapd spkr eq spkr eq vref g m ga m ga m ga v ref key: g = gain a = attenuate m = mute
rev. 0 C2C AD1981A?pecifications parameter min typ max unit analog input input voltage (rms values assume sine-wave input) line_in, aux, cd, phone_in 1 vrms 2.83 vp-p mic_in with 20 db gain 0.1 vrms 0.283 vp-p mic_in with 0 db gain 1 vrms 2.83 vp-p input impedance 1 20 k ? input capacitance 1 5 7.5 pf master volume step size (0 db to ?6.5 db); line_out_l, line_out_r 1.5 db output attenuation range 1 46.5 db step size (0 db to ?6.5 db); mono_out 1.5 db output attenuation range 1 46.5 db step size (0 db to ?6.5 db); hp_out_r, hp_out_l 1.5 db output attenuation range 1 46.5 db mute attenuation of 0 db fundamental 1 80 db programmable gain amplifier?dc step size (0 db to 22.5 db) 1.5 db pga gain range 22.5 db analog mixer?nput gain/amplifiers/attenuators signal-to-noise ratio (snr) cd to line_out 90 db other to line_out 90 db step size (+12 db to ?4.5 db): (all steps tested) mic_in, line_in, cd, aux, phone_in, dac 1.5 db input gain/attenuation range: mic_in, line_in, cd, aux, phone_in, dac 46.5 db digital decimation and interpolation filters 1 pass band 0 0.4 f s hz pass band ripple 0.09 db transition band 0.4 f s 0.6 f s hz stop band 0.6 f s hz stop band rejection ?4 db group delay 16/f s s group delay variation over pass band 0 s standard test conditions unless otherwise noted temperature 25 c digital supply (dv dd ) 3.3 v analog supply (v dd ) 5.0 v sample rate (f s ) 48 khz input signal 1008 hz analog output pass band 20 hz to 20 khz v ih 2.0 v v il 0.8 v v ih ( id0 , id1 ) 4.0 v v il ( id0 , id1 ) 1.0 v dac test conditions calibrated 0 db gain/attenuation relative to full scale 0 db input 10 k ? output load (line_out) 32 ? output load (hp_out) adc test conditions calibrated 0 db gain input ?.0 db relative to full scale
rev. 0 C3C AD1981A specifications parameter min typ max unit analog-to-digital converters resolution 16 bits total harmonic distortion (thd) ?4 db dynamic range (?0 db input thd+n referenced to full scale, a-weighted) 80 85 db signal-to-intermodulation distortion (ccif method) 1 85 db adc crosstalk 1 line inputs (input l, ground r, read r; input r, ground l, read l) ?0 db line_in to other ?00 ?0 db gain error 2 (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.5 db adc offset error 1 5mv digital-to-analog converters resolution 20 bits total harmonic distortion (thd) line_out ?5 db total harmonic distortion (thd) hp_out ?5 db dynamic range (?0 db input thd+n referenced to full scale, a-weighted) 85 90 db signal-to-intermodulation distortion (ccif method) 1 ?00 db gain error (actual output full-scale voltage relative to nominal output full-scale) 10 % interchannel gain mismatch (difference of gain errors) 0.7 db dac crosstalk (input l, zero r, measure r_out; input r, zero l, measure l_out) 1 ?0 db total audible out-of-band energy (measured from 0.6 f s to 20 khz) 1 ?0 db analog output full-scale output voltage; line_out and mono_out 1 vrms 2.83 vp-p output impedance 1 800 ? external load impedance 1 10 k ? output capacitance 1 15 pf external load capacitance 100 pf full-scale output voltage; hp_out (0 db gain) 1 vrms external load capacitance 1 100 pf external load impedance 1 32 ? v ref 2.05 2.25 2.45 v v refout (selectable to 3.70 v nominal) 2.25 v v refout current drive 5ma mute click (muted output minus unmuted midscale dac output) 5mv static digital specifications high level input voltage (v ih ): digital inputs 0.65 dvdd v low level input voltage (v il ) 0.35 dvdd v high level output voltage (v oh ), i oh = 2 ma 0.9 dvdd v low level output voltage (v ol ), i ol = 2 ma 0.1 dvdd v input leakage current ?0 10 a output leakage current ?0 10 a power supply power supply range ?analog (av dd ) 4.65 5.25 v power supply range ?digital (dv dd ) 3.15 3.45 v power dissipation ?5 v/3.3 v 555 mw analog supply current ?5 v (av dd )78ma digital supply current ?3.3 v(dv dd )50ma power supply rejection (100 mv p-p signal @ 1 khz) 1 (at both analog and digital supply pins, both adcs and dacs) 40 db clock specifications 1 input clock frequency 24.576 mhz recommended clock duty cycle 40 50 60 %
rev. 0 C4C AD1981A?pecifications parameter set bits dv dd typ av dd typ unit power-down states 3 (fully active) (no bits value) 47 53 ma adc pr0 39 47 ma dac pr1 32 40 ma adc + dac pr1, pr0 13 34 ma mixer pr2 47 21 ma adc + mixer pr2, pr0 39 16 ma dac + mixer pr2, pr1 32 8 ma adc + dac + mixer pr2, pr1, pr0 13 1 ma standby pr5, pr4, pr3, pr2, pr1, pr0 0 0 ma headphone standby pr6 47 40 ma parameter symbol min typ max unit timing parameters (guaranteed over operating temperature range) reset active low pulsewidth t rst_low 1.0 ms reset inactive to bit_clk start-up delay t rst2clk 162.8 ns sync active high pulsewidth t sync_high 1.3 ms sync low pulsewidth t sync_low 19.5 sync inactive to bit_clk start-up delay t sync2clk 162.8 ns bit_clk frequency 12.288 mhz bit_clk period t clk_period 81.4 ns bit_clk output jitter 1 750 48.84 ps bit_clk high pulsewidth t clk_high 32.56 42 48.84 ns bit_clk low pulsewidth t clk_low 32.56 38 ns sync frequency 48.0 khz sync period t sync_period 20.8 ms setup to falling edge of bit_clk t setup 5 2.5 ns hold from falling edge of bit_clk t hold 5ns bit_clk rise time t riseclk 246ns bit_clk fall time t fallclk 246ns sync rise time t risesync 246ns sync fall time t fallsync 246ns sdata_in rise time t risedin 246ns sdata_in fall time t falldin 246ns sdata_out rise time t risedout 246ns sdata_out fall time t falldout 246ns end of slot 2 to bit_clk, sdata_in low t s2_pdown 0 1.0 ms setup to trailing edge of reset (applies to sync, sdata_out) t setup2rst 15 ns rising edge of reset to hi-z delay t off 25 ns propagation delay 15 ns reset rise time 50 ns output valid delay from rising edge of bit_clk to sdi valid 15 ns notes 1 guaranteed but not tested. 2 measurement reflects main adc. 3 values presented with v refout not loaded. specifications subject to change without notice.
rev. 0 AD1981A C5C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD1981A features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide temperature package package model range description option * AD1981Ajst 0 c to 70 c 48-lead lqfp st-48 * st = thin quad flatpack absolute maximum ratings * (t a = 25 c unless otherwise noted.) power supplies digital (dv dd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +3.6 v analog (av dd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +6.0 v input current (except supply pins) . . . . . . . . . . . . . . . 10 ma signals pins digital input voltage . . . . . . . . . . . . . ?.3 v to dv dd +0.3 v analog input voltage . . . . . . . . . . . . ?.3 v to av dd +0.3 v ambient temperature range (operating) . . . . . . . 0 c to 70 c ambient temperature rating (tqfp package) tamb = tcase ?( pd ca ) tcase = case temperature in c pd = power dissipation in w ja thermal resistance (junction-to-ambient) . . . 76.2 c/w jc thermal resistance (junction-to-case) . . . . . . . 17 c/w ja thermal resistance (case-to-ambient) . . . . . 52.2 c/w storage temperature range . . . . . . . . . . . . 65 c to +150 c * stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
rev. 0 AD1981A C6C pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) line_out_r line_out_l av dd4 av ss4 afilt4 afilt3 afilt2 dv dd1 xtl_in xtl_out dv ss1 sdata_out bit_clk dv ss2 nc = no connect sdata_in dv dd2 sync reset afilt1 v refout v ref av ss1 AD1981A nc av dd1 spdif eapd id1 id0 av ss3 av dd3 nc hp_out_r av ss2 hp_out_l av dd2 mono_out phone_in aux_l aux_r js1 js0 cd_l cd_gnd_ref cd_r mic_in nc line_in_l line_in_r
rev. 0 AD1981A C7C pin function descriptions pin no. mnemonic i/o function digital i/o 2 xtl_in i crystal input (24.576 mhz) or external clock input 3 xtl_out o crystal output 5 sdata_out i ac-link serial data output, AD1981A data input stream 6 bit_clk o/i ac-link bit clock output (12.288 mhz) or bit clock input if secondary mode selected 8 sdata_in o ac-link serial data input, AD1981A data output stream 10 sync i ac-link frame sync 11 reset i ac-link reset, AD1981A master h/w reset 48 spdif o s/pdif output chip selects (these pins can also be used to select an external clock. see table ii.) 45 id0 i chip select input 0 (active low) this pin can also be used as the chain input from a secondary codec. 46 id1 i chip select input 1 (active low) jack sense and eapd 17 js0 i jack sense 0 input 16 js1 i jack sense 1 input 47 eapd o external amp power-down control analog i/o 13 phone_in i phone input. mono input from telephony subsystem speaker phone or handset. 14 aux_l i auxiliary input left channel 15 aux_r i auxiliary input right channel 18 cd_l i cd audio left channel 19 cd_gnd_ref i cd audio analog ground reference for differential cd input 20 cd_ r i cd audio right channel 21 mic_in i microphone input (mono) 23 line_in_l i line in left channel 24 line_in_r i line in right channel 35 line_out_l o line out (front) left channel 36 line_out_r o line out (front) right channel 37 mono_out o monaural output to telephony subsystem speakerphone 39 hp_out_l o headphone left channel output 41 hp_out_r o headphone right channel output filter/reference (these signals are connected to resistors, capacitors, or specific voltages.) 27 v ref o voltage reference filter 28 v refout o voltage reference output 5 ma drive (intended for mic bias and power amp bias) 29 afilt1 o antialiasing filter capacitor?dc right channel 30 afilt2 o antialiasing filter capacitor?dc left channel 31 afilt3 o antialiasing filter capacitor?ixer adc right channel 32 afilt4 o antialiasing filter capacitor?ixer adc left channel power and ground signals 1dv dd1 i digital v dd 3.3 v 4dv ss1 i digital gnd 7dv ss2 i digital gnd 9dv dd2 i digital v dd 3.3 v 25 av dd1 i analog v dd 5.0 v 26 av ss1 i analog gnd 33 av ss4 i analog gnd 34 av dd4 i analog v dd 5.0 v 38 av dd2 i analog v dd 5.0 v 40 av ss2 i analog gnd 43 av dd3 i analog v dd 5.0 v 44 av ss3 i analog gnd no connects 12 nc no connect 22 nc no connect 42 nc no connect
rev. 0 AD1981A C8C indexed control registers reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset x se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 0090h 02h master volume mm x x lmv4 lmv3 lmv2 lmv1 lmv0 rm * x x rmv4 rmv3 rmv2 rmv1 rmv0 8000h 04h headphones volume hpm x x lhv4 lhv3 lhv2 lhv1 lhv0 rm * x x rhv4 rhv3 rhv2 rhv1 rhv0 8000h 06h mono volume mvm x x x x x x x x x x mv4 mv2 mv2 mv1 mv0 8000h 0ch phone volume phm x x x x x x x x x x phv4 phv3 phv2 phv1 phv0 8008h 0eh mic volume mcm x x x x x x x x m20 x mcv4 mcv3 mcv2 mcv1 mcv0 8008h 10h line in volume lm x x llv4 llv3 llv2 llv1 llv0 rm * x x rlv4 rlv3 rlv2 rlv1 rlv0 8808h 12h cd volume cm x x lcv4 lcv3 lcv2 lcv1 lcv0 rm * x x rcv4 rcv3 rcv2 rcv1 rcv0 8808h 16h aux volume am x x lav4 lav3 lav2 lav1 lav0 rm * x x rav4 rav3 rav2 rav1 rav0 8808h 18h pcm out vol om x x lov4 lov3 lov2 lov1 lov0 rm * x x rov4 rov3 rov2 rov1 rov0 8808h 1ah record select x x x x x ls2 ls1 ls0 x x x x x rs2 rs1 rs0 0000h 1ch record gain im x x x lim3 lim2 lim1 lim0 rm * x x x rim3 rim2 rim1 rim0 8000h 20h general purpose x x x x x x x x lpbk x xxxxxx 0000h 26h power-down ctrl/stat eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 x x x x ref anl dac adc 000xh 28h ext? audio id id1 id0 x x rev1 rev0 amap x x x dsa1 dsa0 x spdif x vra x605h 2ah ext? audio stat/ctrl vforce x x x x spcv x x x x spsa1 spsa0 x spdif x vra 0000h 2ch pcm front dac rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h (sr1) 32h pcm l/r adc rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h (sr0) 3ah spdif control v x spsr1 spsr0 l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy /aud pro 2000h 60h eq ctrl eqm mad x x x x x x sym chs bca5 bca4 bca3 bca2 bca1 bca0 8080h lben 62h eq data cfd15 cfd14 cfd13 cfd12 cfd11 cfd10 cfd9 cfd8 cfd7 cfd6 cfd5 cfd4 cfd3 cfd2 cfd1 cfd0 0000h 64h mixer adc, volume mxm x x x lmg3 lmg2 lmg1 lmg0 rm * x x x rmg3 rmg2 rmg1 rmg0 8000h 72h jack sense x x x js js js js1 js0 js1 js0 js1 js0 js1 js0 js1 js0 0000h mt2 mt1 mt0 eqb eqb tmr tmr md md st st int int 74h serial configuration slot regm regm regm x x x chen x x x ints x spal spdz splnk 7001h 16 2 1 0 76h misc control bits dacz x m x dam x fmxe x x mad x mad vrefh vrefd mbg1 mbg0 0000h splt pd st 7ch vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 4144h 7eh vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 5372h notes all registers not shown. bits containing an x are assumed to be reserved. odd registers are reserved, not aliased. reserved registers should not be written to. zeros should be written to bits containing an x. * for ac ?7 compatibility, bit d7 (rm) is only available by setting the msplt bit register 76h. the msplt bit enables separate m ute bits for the left and right channels. if msplt is not set, rm bit has no effect.
rev. 0 AD1981A C9C bit function AD1981A id0 dedicated mic pcm in channel 0 id1 modem line codec support 0 id2 bass and treble control 0 id3 simulated stereo (mono to stereo) 0 id4 headphone out support 1 id5 loudness (bass boost) support 0 id6 18-bit dac resolution 0 id7 20-bit dac resolution 1 id8 18-bit adc resolution 0 id9 20-bit adc resolution 0 reset (index 00h) writing any value to this register performs a register reset, which causes all registers to revert to their default values (exc ept 74h, which forces the serial configuration). reading this register returns the id code of the part and a code for the type of 3d stereo enhancement. id[9:0] identify capability. the id decodes the capabilities of AD1981A based on the following: se[4:0] stereo enhancement: the AD1981A does not provide hardware 3d stereo enhancement (all bits are zeros). master volume register (index 02h) * for ac ?7 compatibility, bit d7 (rm) is only available by setting the msplt bit register 76h. the msplt bit enables separate m ute bits for the left and right channels. if msplt is not set, rm bit has no effect. this register controls the line_out volume controls for both stereo channels and mute bit. each volume subregister contains 5 b its, generating 32 volume levels with 31 steps of 1.5 db each. because ac ?7 defines 6-bit volume registers, to maintain compatibility whenever the d5 or d13 bits are set to ?,?their resp ective lower five volume bits are automatically set to ??by the codec logic. on readback, all lower 5 bits will read ones whenever t hese bits are set to ?. rmv[4:0] right master volume control: the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of ?6.5 db. rm right channel mute: once enabled by the msplt bit in register 76h, this bit mutes the right channel separately from the mm bit. otherwise, this bit will always read ??and will have no effect when set to ?. lmv[4:0] left master volume control: the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of ?6.5 db. mm master volume mute: when this bit is set to ?,?both l/r channels are muted, unless the msplt bit in register 76h is set to ?,?in which case this mute bit will only affect the left channel. xmv5?mv0 mm write readback function 0 00 0000 00 0000 0 db gain 0 00 1111 00 1111 ?2.5 db gain 0 01 1111 01 1111 ?6.5 db gain 0 1x xxxx 01 1111 ?6.5 db gain 1 xx xxxx xx xxxx db gain reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset x se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 0090h reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 02h master volume mm x x lmv4 lmv3 lmv2 lmv1 lmv0 rm * x x rmv4 rmv3 rmv2 rmv1 rmv0 8000h
rev. 0 AD1981A C10C headphones volume register (index 04h) 1 reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 04h headphones volume hpm x x lhv4 lhv3 lhv2 lhv1 lhv0 rm 2 x x rhv4 rhv3 rhv2 rhv1 rhv0 8000h notes 1 this register controls the headphone volume controls for both stereo channels and mute bit. each volume subregister contains 5 bits, generating 32 volume levels with 31 steps of 1.5 db each. because ac 97 defines 6-bit volume registers, to maintain compatibility whenever the d5 or d13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. on readback, all lower 5 bits will read ones when ever these bits are set to 1. 2 for ac 97 compatibility, bit d7 (rm) is only available by setting the msplt bit register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, rm bit has no effect. rhv [4:0] right headphone volume control: the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of 46.5 db. rm right channel mute: once enabled by the msplt bit in register 76h, this bit mutes the right channel separately from the hpm bit. otherwise, this bit will always read 0 and will have no effect when set to 1. lhv [4:0] left headphone volume control: the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of 46.5 db. hpm headphones volume mute: when this bit is set to 1, both l/r channels are muted, unless the msplt bit in register 76h is set to 1, in which case, this mute bit will only affect the left channel. xhv5 xhv0 function hpm write readback function 0 00 0000 00 0000 0 db gain 0 00 1111 00 1111 22.5 db gain 0 01 1111 01 1111 46.5 db gain 0 1x xxxx 01 1111 46.5 db gain 1 xx xxxx xx xxxx db gain mono volume (index 06h) * reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 06h mono volume mvm xxxxx xxxxxmv4mv3mv2mv1mv0 8000h * this register controls the headphone volume controls for both stereo channels and mute bit. each volume subregister contains 5 bits, generating 32 volume levels with 31 steps of 1.5 db each. because ac 97 defines 6-bit volume registers, to maintain compatibility whenever the d5 or d13 bits are set to 1, their respective lower five volume bits are automatically set to 1 by the codec logic. on readback, all lower 5 bits will read ones when ever these bits are set to 1. mv[4:0] mono volume control: the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of 46.5 db. mvm mono volume mute: when this bit is set to 1, the channel is muted. xmv5 xmv0 mvm write readback function 0 00 0000 00 0000 0 db gain 0 00 1111 00 1111 22.5 db gain 0 01 1111 01 1111 46.5 db gain 0 1x xxxx 01 1111 46.5 db gain 1 xx xxxx xx xxxx db gain phone volume (index 0ch) reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d efault 0ch phone volume phmxxxxx xxxxx phv4 phv3 phv2 phv1 phv0 8008h
rev. 0 AD1981A C11C phv[4:0] phone volume: allows setting the phone volume attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to 34.5 db. the default value is 0 db with mute bit enabled. phm phone mute: when this bit is set to 1, the phone channel is muted. mic volume (index 0eh) mcv[4:0] mic volume gain: allows setting the mic volume attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to 34.5 db. the default value is 0 db with mute enabled. m20 mic gain boost: this bit allows setting additional mic gain to increase the microphone sensitivity. the nominal gain boost by default is 20 db; however, bits d0 and d1 (mbg[1:0]) on the miscellaneous control bits register (76h) allow changing the gain boost to 10 db or 30 db if necessary. 0 = disabled; gain = 0 db 1 = enabled; default gain = 20 db (see register 76h, bits d0, d1) mcm mic mute: when this bit is set to 1, the mic channel is muted. line in volume (index 10h) reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 10h line in volume lm x x llv4 llv3 llv2 llv1 llv0 rm * x x rlv4 rlv3 rlv2 rlv1 rlv0 8808h * for ac 97 compatibility, bit d7 (rm) is only available by setting the msplt bit register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, rm bit has no effect. rlv[4:0] line in volume right: allows setting the line in right channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to 34.5 db. the default value is 0 db, mute enabled. rm right channel mute: once enabled by the msplt bit in register 76h, this bit mutes the right channel separately from the lm bit. otherwise, this bit will always read 0 and will have no effect when set to 1. llv[4:0] line in volume left: allows setting the line in left channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to 34.5 db. the default value is 0 db, mute enabled. lm line in mute: when this bit is set to 1, both l/r channels are muted unless the msplt bit in register 76h is set to 1, in which case this mute bit will only affect the left channel. cd volume (index 12h) * for ac 97 compatibility, bit d7 (rm) is only available by setting the msplt bit register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, rm bit has no effect. rcv[4:0] right cd volume: allows setting the cd right channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to 34.5 db. the default value is 0 db, mute enabled. rm right channel mute: once enabled by the msplt bit in register 76h, this bit mutes the right channel separately from the cm bit. otherwise, this bit will always read 0 and will have no effect when set to 1. lcv[4:0] left cd volume: allows setting the cd left channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to 34.5 db. the default value is 0 db, mute enabled. cm cd volume mute: when this bit is set to 1, both l/r channels are muted, unless the msplt bit in register 76h is set to 1, in which case, this mute bit will only affect the left channel. reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0eh mic volume mcm xxxxxxxxm20xmcv4mcv3mcv2mcv1mcv0 8008h reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 12h cd volume cm x x lcv4 lcv3 lcv2 lcv1 lcv0 rm * x x rcv4 rcv3 rcv2 rcv1 rcv0 8808h
rev. 0 AD1981A C12C aux volume (index 16h) reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 16h aux volume am x x lav4 lav3 lav2 lav1 lav0 rm * x x rav4 rav3 rav2 rav1 rav0 8808h * for ac 97 compatibility, bit d7 (rm) is only available by setting the msplt bit register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, rm bit has no effect. rav[4:0] right aux volume: allows setting the aux right channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to 34.5 db. the default value is 0 db, mute enabled. rm right channel mute: once enabled by the msplt bit in register 76h, this bit mutes the right channel separately from the am bit. otherwise, this bit will always read 0 and will have no effect when set to 1. lav[4:0] left aux volume: allows setting the aux left channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to 34.5 db. the default value is 0 db, mute enabled. am aux mute: when this bit is set to 1, both l/r channels are muted unless the msplt bit in register 76h is set to 1, in which case this mute bit will only affect the left channel. pcm out volume (index 18h) reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 18h pcm out vol om x x lov4 lov3 lov2 lov1 lov0 rm * x x rov4 rov3 rov2 rov1 rov0 8808h * for ac 97 compatibility, bit d7 (rm) is only available by setting the msplt bit register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, rm bit has no effect. rov[4:0] right pcm out volume: allows setting the pcm right channel attenuator in 32 volume levels. the lsb repre sents 1.5 db, and the range is +12 db to 34.5 db. the default value is 0 db, mute enabled. rm right channel mute: once enabled by the msplt bit in register 76h, this bit mutes the right channel separately from the om bit. otherwise, this bit will always read 0 and will have no effect when set to 1. lov[4:0] left pcm out volume: allows setting the pcm left channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to 34.5 db. the default value is 0 db, mute enabled. om pcm out volume mute: when this bit is set to 1, both l/r channels are muted unless the msplt bit in register 76h is set to 1, in which case this mute bit will only affect the left channel. volume table (index 0ch to 18h) mute x4...x0 function 0 00000 +12 db gain 0 01000 0 db gain 0 11111 34.5 db gain 1 xxxxx db gain record select control register (index 1ah) reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 1ah record select xxxxxls2ls1ls0 xxxxxrs2rs1rs0 0000h notes used to select the record source independently for right and left. see table for legend. the default value is 0000h, which corresponds to mic in. rs[2:0] right record select ls[2:0] left record select
rev. 0 AD1981A C13C rs1...rs0 right record source 0 mic 1 cd_r 2 muted 3 aux_r 4 line_in_r 5 stereo mix (r) 6 mono mix 7 phone_in ls1...ls0 left record source 0 mic 1 cd_l 2 muted 3 aux_l 4 line_in_l 5 stereo mix (l) 6 mono mix 7 phone_in record gain (index 1ch) * for ac 97 compatibility, bit d7 (rm) is only available by setting the msplt bit register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, rm bit has no effect. rim[3:0] right input mixer gain control: each lsb represents 1.5 db, 0000 = 0 db, and the range is 0 db to 22.5 db. rm right channel mute: once enabled by the msplt bit in register 76h, this bit mutes the right channel separately from the im bit. otherwise, this bit will always read 0 and will have no effect when set to 1. lim[3:0] left input mixer gain control: each lsb represents 1.5 db, 0000 = 0 db, and the range is 0 db to 22.5 db. im input mute: when this bit is set to 1, both l/r channels are muted unless the msplt bit in register 76h is set to 1, in which case this mute bit will only affect the left channel. im xim3...xim0 function 0 1111 +22.5 db gain 0 0000 0 db gain 1 xxxxx db gain general purpose register (index 20h) * reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 20h general purpose xxxxxxxx lpbk xxxxxxx 0000h * this register should be read before writing to generate a mask for only the bit(s) that need to be changed. lpbk loop-back control: adc/dac digital loop-back mode reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 1ch record gain im x x x lim3 lim2 lim1 lim0 rm * x x x rim3 rim2 rim1 rim0 8000h
rev. 0 AD1981A C14C power-down control/status register (index 26h) notes the ready bits are read only; writing to ref, anl, dac, adc will have no effect. these bits indicate the status for the AD1981A subsections. if the bit is a 1 then that subsection is ready . ready is defined as the subsection able to perform in its nominal state. adc adc sections ready to transmit data dac dac sections ready to accept data anl analog amplifiers, attenuators, and mixers ready ref voltage references, v ref and v refout up to nominal level pr[6:0] codec power-down modes. the first 3 bits are to be used individually rather than in combination with each other. pr3 can be used in combination with pr2 or by itself. the mixer and reference cannot be powered down via pr3 unless the adcs and dacs are also powered down. nothing else can be powered up until the reference is up. pr5 has no effect unless all adcs, dacs, and the ac link are powered down. the reference and mixer can be either up or down, but all power-up sequences must be allowed to run to completion before pr5 and pr4 are both set. in multiple-codec systems, the master codec s pr5 and pr4 bits control the slave codec. pr5 is also effective in the slave codec if the master s pr5 bit is clear, but the pr4 bit has no effect except to enable or disable pr5. eapd external audio power-down control: controls the state of the eapd pin eapd = 0 sets the eapd pin low, enabling an external power amplifier (reset default). eapd = 1 sets the eapd pin high, shutting the external power amplifier off. power-down state set bits adcs and input mux power-down pr0 dacs power-down pr1 analog mixer power-down (v ref and v refout on) pr1, pr2 analog mixer power-down (v ref and v refout off) pr0, pr1, pr3 ac-link interface power-down pr4 internal clocks disabled pr0, pr1, pr4, pr5 adc and dac power down pr0, pr1 v ref standby mode pr0, pr1, pr2, pr4, pr5 total power-down pr0, pr1, pr2, pr3, pr4, pr5 headphone amp power in standby pr6 extended audio id register (index 28h) reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d efault 28h ext d audio id id1 id0 x x rev1 rev0 amap x x x dsa1 dsa0 x spdif x vra x605h the extended audio id register identifies which extended audio features are supported. a non-zero extended audio id value indic ates one or more of the extended audio features are supported. reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 26h power-down cntrl/stat eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 xxxxrefanldacadc000xh
rev. 0 AD1981A C15C vra variable rate pcm audio support: (read-only) this bit returns a 1 when read to indicate that variable rate pcm audio is supported. spdif spdif support: (read-only) this bit returns a 1 when read to indicate that spdif transmitter is supported (iec958). dsa[1:0] dac slot assignments: (read/write) (reset default = 00) 00 dacs 1, 2 = 3 and 4 01 dacs 1, 2 = 7 and 8 10 dacs 1, 2 = 6 and 9 11 dacs 1, 2 = 10 and 11 amap slot dac mappings based on codec id: (read only) this bit returns a 1 when read to indicate that slot/dac mappings based on codec id is supported. rev[1:0] rev[1, 0] = 01 indicates codec is ac 97 revision 2.2-compliant (read-only). id[1:0] indicates codec configuration: (read-only) 00 = primary 01, 10, 11 = secondary extended audio status and control register (index 2ah) * the extended audio status and control register is a read/write register that provides status and control of the extended audio features. vra variable rate audio: (read/write) vra = 0, sets fixed sample rate audio at 48 khz (reset default). vra = 1, enables variable rate audio mode (enables sample rate registers and slotreq signaling). spdif spdif transmitter subsystem enable/disable bit: (read/write) spdif = 1 enables the spdif transmitter. spdif = 0 disables the spdif transmitter (default). this bit is also used to validate that the spdif transmitter output is actually enabled. the spdif bit is only allowed to be set high if the spdif pin (48) is pulled down at power-up enabling the codec transmitter logic. if the spdif pin is floating or pulled high at power-up, the transmitter logic is disabled and this bit therefore returns a low, indicating that the spdif transmitter is not available. this bit must always be read back to verify that the spdif transmitter is actually enabled. spsa[1:0] spdif slot assignment bits: (read/write) these bits control the spdif slot assignment and respective defaults, depending on the codec id configuration. spcv spdif configuration valid: (read-only) indicates the status of the spdif transmitter subsystem, enabling the driver to determine if the currently programmed spdif configuration is supported. spcv is always valid, independent of the spdif-enable bit status. spcv = 0 indicates current spdif configuration {spsa, spsr, dac slot rate, drs} is not valid (not supported). spcv = 1 indicates current spdif configuration {spsa, spsr, dac slot rate, drs} is valid (supported). vforce validity force bit: (reset default = 0) when asserted, this bit forces the spdif stream validity flag (bit 28 within each spdif l/r subframe) to be controlled by the v bit (d15) in register 3ah (spdif control register). vforce = 0 and v = 0; the validity bit is managed by the codec error detection logic. vforce = 0 and v = 1; the validity bit is forced high, indicating subframe data is invalid. vforce = 1 and v = 0; the validity bit is forced low, indicating subframe data is valid. vforce = 1 and v = 1; the validity bit is forced high, indicating subframe data is invalid. reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 2ah ext d audio stat/ctrl vforce xxxx spcv xxxx spsa1 spsa0 x spdif x vra 0000h
rev. 0 AD1981A C16C ac 97 2.2 amap-compliant default spdif slot assignments codec id function spsa = 00 spsa = 01 spsa = 10 spsa = 11 00 2-ch primary w/spdif 3 and 4 7 and 8 [default] 6 and 9 10 and 11 00 4-ch primary w/spdif 3 and 4 7 and 8 6 and 9 [default] 10 and 11 00 6-ch primary w/spdif 3 and 4 7 and 8 6 and 9 10 and 11 [default] 01 +2-ch secondary w/spdif 3 and 4 7 and 8 6 and 9 [default] 01 +4-ch secondary w/spdif 3 and 4 7 and 8 6 and 9 10 and 11 [default] 10 +2-ch secondary w/spdif 3 and 4 7 and 8 6 and 9 [default] 10 +4-ch secondary w/spdif 3 and 4 7 and 8 6 and 9 10 and 11 [default] 11 +2-ch secondary w/spdif 3 and 4 7 and 8 6 and 9 10 and 11 [default] pcm front dac rate register (index 2ch) * this read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in hz. sr[15:0] sample rate: the sampling frequency range is from 7 khz (1b58h) to 48 khz (bb80h) in 1 hz increments. if 0 is written to vra, then the sample rate is reset to 48k. pcm adc rate register (index 32h) reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 32h pcm l/r adc rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h this read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in hz. sr[15:0] sample rate: the sampling frequency range is from 7 khz (1b58h) to 48 khz (bb80h) in 1 hz increments. if 0 is written to vra, then the sample rate is reset to 48k. spdif control register (index 3ah) reg. num. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 3ah spdif control v x spsr1 spsr0 l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy /aud pro 2000h * register 3ah is a read/write register that controls spdif functionality and manages bit fields propagated as channel status (or subframe in the v case). with the exception of v, this register should only be written to when the spdif transmitter is disabled (spdif bit in register 2ah is 0 ). this ensures that control and status information start up correctly at the beginning of spdif transmission. pro professional: 1 indicates professional use of channel status, 0 indicates consumer. /aud non-audio: 1 indicates data is non-pcm format, 0 data is pcm. copy copyright: 1 indicates copyright is asserted, 0 copyright is not asserted. pre pre-emphasis: 1 indicates filter pre-emphasis is 50/15 msec, 0 pre-emphasis is none. cc[6:0] category code: programmed according to iec standards, or as appropriate. l generation level: programmed according to iec standards, or as appropriate. spsr[1:0] spdif transmit sample rate: spsr[1:0] = 00 transmit sample rate = 44.1 khz spsr[1:0] = 01 reserved spsr[1:0] = 10 transmit sample rate = 48 khz (reset default) spsr[1:0] = 11 not supported v validity: this bit affects the validity flag (bit 28 transmitted in each spdif l/r subframe) and enables the spdif transmitter to maintain connection during error or mute conditions. v = 1 each spdif subframe (l + r) has bit 28 set to 1. this tags both samples as invalid. v = 0 each spdif subframe (l + r) has bit 28 set to 0 for valid data and 1 for invalid data (error condition). note that when v = 0, asserting the vforce bit (d15) in register 2ah (ext d audio stat/ctrl) will force the validity flag low, marking both samples as valid. reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 2ch pcm front dac rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h
rev. 0 AD1981A C17C eq control register (index 60h) reg. num. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 60h eqctrl eqm mad lben xxxxxxsymchs bca5 bca4 bca3 bca2 bca1 bca0 8080h * register 60h is a read/write register that controls the equalizer functionality and data setup. the register also contains the biquad and coefficient address pointer, which is used in conjunction with the eq data register (78h) to set up the equalizer coefficients. the reset default disables the equalizer function until the coefficients can be properly set up by the software and sets the sy mmetry bit to allow equal coefficients for left and right channels. bca[5,0] biquad and coefficient address pointer: biquad 0 coef a0 bca[5,0] = 011011 biquad 0 coef a1 bca[5,0] = 011010 biquad 0 coef a2 bca[5,0] = 011001 biquad 0 coef b1 bca[5,0] = 011101 biquad 0 coef b2 bca[5,0] = 011100 biquad 1 coef a0 bca[5,0] = 100000 biquad 1 coef a1 bca[5,0] = 011111 biquad 1 coef a2 bca[5,0] = 011110 biquad 1 coef b1 bca[5,0] = 100010 biquad 1 coef b2 bca[5,0] = 100001 biquad 2 coef a0 bca[5,0] = 100101 biquad 2 coef a1 bca[5,0] = 100100 biquad 2 coef a2 bca[5,0] = 100011 biquad 2 coef b1 bca[5,0] = 100111 biquad 2 coef b2 bca[5,0] = 100110 biquad 3 coef a0 bca[5,0] = 101010 biquad 3 coef a1 bca[5,0] = 101001 biquad 3 coef a2 bca[5,0] = 101000 biquad 3 coef b1 bca[5,0] = 101100 biquad 3 coef b2 bca[5,0] = 101011 biquad 4 coef a0 bca[5,0] = 101111 biquad 4 coef a1 bca[5,0] = 101110 biquad 4 coef a2 bca[5,0] = 101101 biquad 4 coef b1 bca[5,0] = 110001 biquad 4 coef b2 bca[5,0] = 110000 biquad 5 coef a0 bca[5,0] = 110100 biquad 5 coef a1 bca[5,0] = 110011 biquad 5 coef a2 bca[5,0] = 110010 biquad 5 coef b1 bca[5,0] = 110110 biquad 5 coef b2 bca[5,0] = 110101 biquad 6 coef a0 bca[5,0] = 111001 biquad 6 coef a1 bca[5,0] = 111000 biquad 6 coef a2 bca[5,0] = 110111 biquad 6 coef b1 bca[5,0] = 111011 biquad 6 coef b2 bca[5,0] = 111010
rev. 0 AD1981A C18C chs channel select: chs = 0 selects left channel coefficients data block chs = 1 selects right channel coefficients data block sym symmetry: when set to 1, this bit indicates that the left and right channel coefficients are equal. this shortens the coefficients setup sequence since only the left channel coefficients need to be addressed and set up (the right channel coefficients are fetched from the left channel memory). mad mixer adc loop-back enable: enables mixer adc data to be summed into pcm stream. lben 0 = no loop-back allowed (default) 1 = enable loop-back eqm equalizer mute: when set to 1, this bit disables the equalizer function (allows all data pass-through). the reset default sets this bit to 1, disabling the equalizer function until the biquad coefficients can be properly set. eq data register (index 62h) reg. num. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 62h eq data cfd15 cfd14 cfd13 cfd12 cfd11 cfd10 cfd9 cfd8 cfd7 cfd6 cfd5 cfd4 cfd3 cfd2 cfd1 cfd0 0000h this read/write register is used to transfer eq biquad coefficients into memory. the register data is transferred to, or retrieved from, the address pointed by the bca bits in the eq cntrl register (60h). dat a will only be written to memory if the eqm bit (register 60h bit 15) is asserted. dacs should be powered down when new eq coefficients are being added. cfd[15:0] coefficient data: the biquad coefficients are fixed point format values with 16 bits of resolution. the cfd15 bit is the msb, and the cfd0 bit is the lsb. mixer adc, input gain register (index 64h) * for ac 97 compatibility, bit d7 (rm) is only available by setting the msplt bit in register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, rm bit has no effect. rmg[3:0] right mixer gain control: this register controls the gain into the mixer adc, from 0 db to a maximum gain of +22.5 db. the least significant bit represents 1.5 db. rm right channel mute: once enabled by the msplt bit in register 76h, this bit mutes the right channel separately from the im bit. otherwise, this bit will always read 0 and will have no effect when set to 1. lmg[3:0] left mixer gain control: this register controls the gain into the mixer adc, from 0 db to a maximum gain of +22.5 db. the least significant bit represents 1.5 db. mxm mixer gain mute: 0 = unmuted, 1 = muted or db gain. mxm xmg3...xmg0 function 0 1111 +22.5 db gain 0 0000 0 db gain 1 xxxxx db gain jack sense/audio interrupt/status register (index 72h) reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 72h jack sense x x x js js js js1 js0 js1 js0 js1 js0 js1 js0 js1 js0 0000h mt2 mt1 mt0 eqb eqb tmr tmr md md st st int int all register bits are read/write except for js0st and js1st, which are read only. reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d efault 64h mixer volume mxm x x x lmg3 lmg2 lmg1 lmg0 rm * x x x rmg3 rmg2 rmg1 rmg0 8000h
rev. 0 AD1981A C19C js0int indicates pin js0 has generated an interrupt. remains set until the software services js0 interrupt, i.e., js0 isr, should clear this bit by writing a 0 to it. note that the interrupt to the system is actually an or combination of this bit and js1int. also note that the actual interrupt implementation is selected by the ints bit (reg 74h). it is also possible to generate a software system interrupt by writing a 1 to this bit. js1int indicates pin js1 has generated an interrupt. remains set until the software services js1 interrupt, i.e., js1 isr should clear this bit by writing a 0 to it. see js0int description above for additional details. js0st js0 state: this bit always reports the logic state of js0 pin. js1st js1 state: this bit always reports the logic state of js1 pin. js0md js0 mode: this bit selects the operation mode for the js0 pin. 0 = jack sense mode (default) 1 = interrupt mode js1md js1 mode: this bit selects the operation mode for the js1 pin. 0 = jack sense mode (default) 1 = interrupt mode js0tmr js0 timer enable: if this bit is set to a 1, js0 must be high for greater than 250 ms to be recognized. js1tmr js1 timer enable: if this bit is set to a 1, js1 must be high for greater than 250 ms to be recognized. js0eqb js0 eq bypass enable: this bit enables js0 to control the eq bypass. when this bit is set to 1, js0 = 1 will cause the eq to be bypassed. js1eqb js1 eq bypass enable: this bit enables js1 to control the eq bypass. when this bit is set to 1, js1 = 1 will cause the eq to be bypassed. jsmt[2,0] js mute enable selector: these 3 bits select and enable the jack sense muting action (see table i).
rev. 0 AD1981A C20C table i. jack sense mute table jsmt [2:0] ref js1 js0 jsmt2 jsmt1 jsmt0 h.p. line mono notes headphone line out out out out

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** ** ** fmute = output is forced to mute independent of the respective volume register setting. active = output is not muted and its status is dependent on the respective volume register setting. out = nothing plugged into the jack and, therefore, the js status is low (via the load resistor pull-down). in = jack has plug inserted and therefore the js status is high (via the codec js internal pull-up). serial configuration (index 74h) this register is not reset when the reset register (register 00h) is written. splnk spdif link: this bit enables the spdif to link with the dac for data requesting. 0 = spdif and dac are not linked. 1 = spdif and dac are linked and receive same data requests (reset default). spdz spdif dacz: 0 = repeat last sample out the spdif stream if fifo underruns (reset default). 1 = forces midscale sample out the spdif stream if fifo underruns. spal spdif adc loop around: 0 = spdif transmitter is connected to the ac-link stream (reset default). 1 = spdif transmitter is connected to the digital adc stream, not the ac-link. ints interrupt mode select: this bits selects the js interrupt implementation path. 0 = bit 0 slot 12 (modem interrupt) 1 = slot 6 valid bit (mic adc interrupt) chen chain enable: this bit enables chaining of a slave codec sdata_in stream into the id0 pin (45). 0 = disable chaining (reset default) 1 = enable chaining into id0 pin reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 74h serial configuration slot16 regm2 regm1 regm0 x x x chen x x x ints x spal spdz splnk 7001h
rev. 0 AD1981A C21C regm0 master codec register mask regm1 slave 1 codec register mask regm2 slave 2 codec register mask slot16 enable 16-bit slot mode. slot16 makes all ac link slots 16 bits in length, formatted into 16 slots. this is a preferred mode for dsp serial port interfacing. miscellaneous control bits (index 76h) reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 76h misc control bits dacz x msplt x dam x fmxe x x madpd x madst vrefh vrefd mbg1 mbg0 0000h mbg[1:0] mic boost gain change register: these two bits allow changing the mic preamp gain from the nominal 20 db gain. note: this gain setting only takes effect while bit d6 (m20) on the mic volume register (0eh) is set to 1. otherwise the mic boost block has a gain of 0 db. 00 = 20 db gain (reset default) 01 = 10 db gain 10 = 30 db gain 11 = reserved vrefd v refout disable: disables v refout placing it into high zout mode. note that this bit overrides the vrefh bit selection (see below). 0 = v refout pin is driven by the internal reference (reset default) 1 = v refout pin is placed into high zout mode vrefh v refout high: changes v refout from 2.25 v to 3.70 v for mic bias applications. 0 = v refout pin is set to 2.25 v output (reset default) 1 = v refout pin is set to 3.70 v output madst mixer adc status bit: indicates status of mixer digitizing adc (l/r channels) 0 = mixer adc not ready 1 = mixer adc is ready madpd mixer adc power-down: controls power-down for mixer digitizing adc. 0 = mixer adc is powered-on (default) 1 = mixer adc is powered-down fmxe front dac into mixer enable: controls the front (main) dac to mixer mute switches. 0 = front dac outputs are allowed to sum into the mixer (reset default) 1 = front dac outputs are muted into the mixer (blocked) dam digital audio mode: pcm dac outputs bypass the analog mixer and are sent directly to the codec output. msplt mute split: allows separate mute control bits for master, headphone, line_in, cd, aux, and pcm volume control registers as well as record gain register and mixer adc volume. 0 = both left and right channel mutes are controlled by bit 15 in the respective registers (reset default) 1 = bit 15 affects only the left channel mute and bit 7 affects only the right channel mute dacz dac zero-fill: (versus repeat) if dac is starved for data. 0 = when dac is filled with repeat data 1 = when dac is filled with zeros (reset default) vendor id registers (index 7ch) reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 7ch vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 4144h s[7:0] this register is ascii encoded to a f[7:0] this register is ascii encoded to d
rev. 0 AD1981A C22C vendor id registers (index 7eh) reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 7eh vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 5372h t[7:0] this register is ascii encoded to s rev[7:0] vendor-specific revision number: the AD1981A assigns 71h to this field. table ii. codec id and external clock selection id1 ido codec id codec clocking source 1 1 (00) primary 24.576 mhz (local xtal or external into xtl_in) 1 0 (01) secondary 12.288 mhz (external into bit_clk) 0 1 (00) primary 48.000 mhz (external into xtl_in) 0 0 (00) primary 14.31818 mhz (external into xtl_in) note that the id# pins have weak internal pull-ups and are inverted internally.
rev. 0 AD1981A C23C outline dimensions dimensions shown in millimeters and (inches) 48-lead thin plastic quad (lqfp) (st-48) top view (pins down) 1 12 13 25 24 36 37 48 0.27 (0.0106) 0.22 (0.0087) 0.17 (0.0067) 0.50 (0.0197) bsc 7.00 (0.2756) bsc sq 9.00 (0.3543) bsc sq seating plane 1.60 (0.0630) max 0.75 (0.0295) 0.60 (0.0236) 0.45 (0.0177) view a 7 3.5 0 0.20 (0.0079) 0.09 (0.0035) 1.45 (0.0571) 1.40 (0.0551) 1.35 (0.0531) 0.15 (0.0059) 0.05 (0.0020) coplanarity 0.08 (0.0031) max view a rotated 90 ccw gage plane 0.25 (0.0098) pin 1 indicator controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-026-bbc
C24C c02650C0C5/02(0) printed in u.s.a. printed in u.s.a.

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